/**
 *******************************************************************************
 * @file        A94B114.h
 * @author      ABOV R&D Division
 * @brief       A94B114 Header File
 *
 * Copyright 2020 ABOV Semiconductor Co.,Ltd. All rights reserved.
 *
 * This file is licensed under terms that are found in the LICENSE file
 * located at Document directory.
 * If this file is delivered or shared without applicable license terms,
 * the terms of the BSD-3-Clause license shall be applied.
 * Reference: https://opensource.org/licenses/BSD-3-Clause
 ******************************************************************************/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __A94B114_H_
#define __A94B114_H_

//----------------------------------------------------- 0x80

__sfr __at(0x80) P0; // P0 Data Reg.
/*  BIT Register  */
/* P0 */
__sbit __at(0x80) P00;
__sbit __at(0x81) P01;
__sbit __at(0x82) P02;
__sbit __at(0x83) P03;
__sbit __at(0x84) P04;
__sbit __at(0x85) P05;
__sbit __at(0x86) P06;
__sbit __at(0x87) P07;

__sfr __at(0x81) SP;
__sfr16 __at(0x8382) DPTR0;
__sfr __at(0x82) DPL;
__sfr __at(0x83) DPH;
__sfr16 __at(0x8382) DPTR1;
__sfr __at(0x82) DPL1;
__sfr __at(0x83) DPH1;
__sfr __at(0x84) DBTSR;
__sfr __at(0x85) BITCNT;
__sfr __at(0x86) BITCR;
__sfr __at(0x87) PCON;
//----------------------------------------------------- 0x88
__sfr __at(0x88) P1; // P0 Data Reg.
/*  BIT Register  */
__sbit __at(0x8D) P15;
__sbit __at(0x8C) P14;
__sbit __at(0x8B) P13;
__sbit __at(0x8A) P12;
__sbit __at(0x89) P11;
__sbit __at(0x88) P10;

__sfr __at(0x89) LVIR;    // Low voltage Indicator Reg.
__sfr __at(0x8A) IOFFSET; // Interrupt Offset Reg.
__sfr __at(0x8B) EIPOL0;  // External Interrupt Polarity Reg. 0
__sfr __at(0x8C) EIPOL1;  // External Interrupt Polarity Reg. 1
__sfr __at(0x8D) WDTMR;   // Watch Dog Timer Mode Reg.
__sfr __at(0x8E) WDTR;    // Watch Dog Timer Data Reg.
__sfr __at(0x8E) WDTCR;
__sfr __at(0x8F) SYSCON_AR; // System control Access Reg.
//----------------------------------------------------- 0x90
__sfr __at(0x90) P2; // P2 Data Reg.
__sbit __at(0x93) P23;
__sbit __at(0x92) P22;
__sbit __at(0x91) P21;
__sbit __at(0x90) P20;

__sfr __at(0x92) T0CR;   // Timer 0 Control Reg.
__sfr __at(0x93) T0CNT;  // Timer 0 Counter Reg.
__sfr __at(0x94) T0DR;   // Timer 0 Data Reg.
__sfr __at(0x94) T0CDR;  // Timer 0 Capture Data Reg.
__sfr __at(0x95) ADCM;   // A/D Converter Mode 0 Reg.
__sfr __at(0x96) ADCM1;  // A/D Converter Mode 1 Reg.
__sfr16 __at(0x9796) ADCR; // A/D Converter Data
__sfr __at(0x96) ADCRL;  // A/D Converter Data Low Reg.
__sfr __at(0x97) ADCRH;  // A/D Converter Data Low Reg.
//----------------------------------------------------- 0x98
__sfr __at(0x98) RSFR; // A/D Converter Data Low Reg.
__sfr __at(0x9A) ILVL; // Interrupt nesting Level Indicate Reg.
__sfr __at(0x9B) P0IO; // P0 Direction Reg.
__sfr __at(0x9C) P0PU; // P0 Pull-up Reg.
__sfr __at(0x9D) P0OD; // P0 Open-drain Selection Reg.
__sfr __at(0x9E) P0DB; // P0 De-bounce Time selection Reg.
//----------------------------------------------------- 0xA0
__sfr __at(0xA0) IRQ0;
__sbit __at(0xA0) CMP_INT_F;   // Comparator Interrput FLAG
__sbit __at(0xA1) EIN10_INT_F; // External Interrupt 10 FLAG
__sbit __at(0xA2) EIN11_INT_F; // External Interrupt 11 FLAG
__sbit __at(0xA3) EIN12_INT_F; // External Interrupt 12 FLAG
__sbit __at(0xA4) EINT_INT_F;  // External Interrupt 0~2 FLAG

__sfr __at(0xA2) EO;
__sfr __at(0xA3) P1IO; // P1 Direction Reg.
__sfr __at(0xA4) P1PU; // P1 Pull-up Reg.
__sfr __at(0xA5) P1OD; // P1 Open-drain Selection Reg.
__sfr __at(0xA6) P1DB; // P1 De-bounce Time Selection Reg.
//----------------------------------------------------- 0xA8
__sfr __at(0xA8) IRQ1;
__sbit __at(0xA8) I2C_INT_F;     // I2C Interrupt FLAG
__sbit __at(0xA9) UART_RX_INT_F; //  UART RX Interrupt FLAG
__sbit __at(0xAA) UART_TX_INT_F; //  UART TX Interrupt FLAG
__sbit __at(0xAB) CRC_INT_F;     // CRC Interrupt FLAG
__sbit __at(0xAC) T0_INT_F;      // T0 Interrupt FLAG
__sbit __at(0xAD) T1_INT_F;      // T1 Interrupt FLAG
__sbit __at(0xAE) T2_INT_F;      // T2 Interrupt FLAG

__sfr __at(0xAA) LDOCR; // Low Drop Convertor Control Reg.
__sfr __at(0xAB) P2IO;  // P2 Direction Reg.
__sfr __at(0xAC) P2PU;  // P2 Pull-up Reg.
__sfr __at(0xAD) P2OD;  // P2 Open-drain Selection Reg.
__sfr __at(0xAE) P2DB;  // P2 De-bounce Time Selection Reg.
//----------------------------------------------------- 0xB0
__sfr __at(0xB0) IRQ2;
__sbit __at(0xB0) ADC_INT_F; // ADC Interrupt FLAG
__sbit __at(0xB1) WDT_INT_F; // WDT Interrupt FLAG
__sbit __at(0xB2) BIT_INT_F; // BIT Interrupt FLAG
__sbit __at(0xB3) LVI_INT_F; // LVI Interrupt FLAG

__sfr16 __at(0xB4B3) P0FSR; // P0 Function Selection Reg.
__sfr __at(0xB3) P0FSRL;  // P0 Function Selection Low Reg.
__sfr __at(0xB4) P0FSRH;  // P0 Function Selection High Reg.
__sfr16 __at(0xB6B5) P1FSR; // P1 Function Selection Reg.
__sfr __at(0xB5) P1FSRL;  // P1 Function Selection Low Reg.
__sfr __at(0xB6) P1FSRH;  // P1 Function Selection High Reg.
__sfr __at(0xB7) P2FSR;   // P2 Function Selection Reg.
//----------------------------------------------------- 0xB8
__sfr __at(0xB8) IE; // Interrupt Enable Reg.
__sfr __at(0xB8) IE0;
__sbit __at(0xB8) CMP_INT_EN;   // Comparator Interrput Enable
__sbit __at(0xB9) EIN10_INT_EN; // External Interrupt 10 Enable
__sbit __at(0xBA) EIN11_INT_EN; // External Interrupt 11 Enable
__sbit __at(0xBB) EIN12_INT_EN; // External Interrupt 12 Enable
__sbit __at(0xBC) EINT_INT_EN;  // External Interrupt 0~2 Enable
__sbit __at(0xBF) EA;           // Grobal Interrupt Enable

__sfr16 __at(0xBBBA) T1CR;  // Timer 1 Control Reg.
__sfr __at(0xBA) T1CRL;   // Timer 1 Control Low Reg.
__sfr __at(0xBB) T1CRH;   // Timer 1 Control High Reg.
__sfr16 __at(0xBDBC) T1ADR; // Timer 1 A Data Reg.
__sfr __at(0xBC) T1ADRL;  // Timer 1 A Data Low Reg.
__sfr __at(0xBD) T1ADRH;  // Timer 1 A Data High Reg.
__sfr16 __at(0xBFBE) T1BDR; // Timer 1 B Data Reg.
__sfr __at(0xBE) T1BDRL;  // Timer 1 B Data Low Reg.
__sfr __at(0xBF) T1BDRH;  // Timer 1 B Data High Reg.
//----------------------------------------------------- 0xC0
__sfr __at(0xC0) IE1;             // Interrupt Enable Reg. 1
__sbit __at(0xC0) I2C_INT_EN;     // I2C Interrupt Enable
__sbit __at(0xC1) UART_RX_INT_EN; // UART RX Interrupt Enable
__sbit __at(0xC2) UART_TX_INT_EN; // UART TX Interrupt Enable
__sbit __at(0xC3) CRC_INT_EN;     // CRC Interrupt Enable
__sbit __at(0xC4) T0_INT_EN;      // T0 Interrupt Enable
__sbit __at(0xC5) T1_INT_EN;      // T1 Interrupt Enable
__sbit __at(0xC6) T2_INT_EN;      // T2 Interrupt Enable

__sfr16 __at(0xC3C2) T2CR;  // Timer 2 Control Reg.
__sfr __at(0xC2) T2CRL;   // Timer 2 Control Low Reg.
__sfr __at(0xC3) T2CRH;   // Timer 2 Control High Reg.
__sfr16 __at(0xC5C4) T2ADR; // Timer 2 A Data Reg.
__sfr __at(0xC4) T2ADRL;  // Timer 2 A Data Low Reg.
__sfr __at(0xC5) T2ADRH;  // Timer 2 A Data High Reg.
__sfr16 __at(0xC7C6) T2BDR; // Timer 2 B Data Reg.
__sfr __at(0xC6) T2BDRL;  // Timer 2 B Data Low Reg.
__sfr __at(0xC7) T2BDRH;  // Timer 2 B Data High Reg.
//----------------------------------------------------- 0xC8
__sfr __at(0xC8) IE2;       // Interrupt Enable Reg. 2
__sbit __at(0xC8) ADC_INT_EN;   // ADC Interrupt Enable
__sbit __at(0xC9) WDT_INT_EN;  // WDT Interrupt Enable
__sbit __at(0xCA) BIT_INT_EN;  // BIT Interrupt Enable
__sbit __at(0xCB) LVI_INT_EN; // LVI Interrupt Enable

__sfr __at(0xC9) EIFLAG;  // External Interrupt flag Reg.
__sfr16 __at(0xCDCC) T1CDR; // Timer 1 C Data Reg.
__sfr __at(0xCC) T1CDRL;  // Timer 1 C Data Low Reg.
__sfr __at(0xCD) T1CDRH;   // Timer 1 C Data High Reg.
__sfr16 __at(0xCFCE) T1DDR;  // Timer 1 D Data Reg.
__sfr __at(0xCE) T1DDRL;   // Timer 1 D Data Low Reg.
__sfr __at(0xCF) T1DDRH;  // Timer 1 D Data High Reg.

//----------------------------------------------------- 0xD0
__sfr __at(0xD0) PSW;  // Program Status word Reg.
__sbit __at(0xD7) CY;  // Carry Flag
__sbit __at(0xD6) AC;  // Auxiliary Carry Flag
__sbit __at(0xD5) F0;  // General Purpose User-definable Flag
__sbit __at(0xD4) RS1; // Register Bank Select bit 1
__sbit __at(0xD3) RS0; // Register Bank Select bit 0
__sbit __at(0xD2) OV;  // Overflow Flag
__sbit __at(0xD1) F1;  // User-definable Flag (used Multiply@ keil compiler)
__sbit __at(0xD0) P;   // Parity Flag

__sfr __at(0xD6)  CMPCR; // Comparator Control Reg.
__sfr __at(0xD7)  CMPTR; // Comparator Trigger Control Reg.
//----------------------------------------------------- 0xD8
__sfr __at(0xD8)  OSCCR;  // Oscillator Control Reg.
__sfr __at(0xD9)  SCCR;   // System Clock Control Reg.
__sfr __at(0xDE)  CMPDBT; // Comparator De-bounce Time Reg.
//----------------------------------------------------- 0xE0
__sfr __at(0xE0) ACC;    // Accumulator A Reg.
__sfr __at(0xE1)  UCTRL1; // USART	R/W 8'b0000_0000	USART Control Register 1
__sfr __at(0xE2)  UCTRL2 ; // USART	R/W 8'b0000_0000	USART Control Register 2
__sfr __at(0xE3)  UCTRL3 ; // USART	R/W 8'b0000_0000	USART Control Register 3
__sfr __at(0xE4)  USTAT;  // USART	R/W 8'b1000_0000	USART Status Register
__sfr __at(0xE5)  UBAUD;  // USART	R/W 8'b1111_1111	USART BaudRate Register
__sfr __at(0xE6)  UDATA;  // USART	R/W 8'b0000_0000	USART Data Register
//----------------------------------------------------- 0xE8
__sfr __at(0xE8)  IP;  // Interrupt Priority Reg.
__sfr __at(0xE8)  IP0; // Interrupt Priority Reg. 0
__sfr __at(0xE9)  IP1; // Interrupt Priority Reg. 1
__sfr __at(0xEA)  IP2; // Interrupt Priority Reg. 2

__sfr __at(0xEB)  UCTRL4; // USART	R/W 8'b0000_0000	USART Control Register 4
__sfr __at(0xEC)  FPCR;   // USART	R/W 8'b0000_0000	USART Floating Point Register
//----------------------------------------------------- 0xF0
__sfr __at(0xF0)  B;
//----------------------------------------------------- 0xF8

__sfr __at(0xF8) I2CSR;    // I2C Status Register
__sfr __at(0xF9) I2CMR;    // I2C Mode Control Register
__sfr __at(0xFA) I2CSCLLR; // I2C SCL Low Period Register
__sfr __at(0xFB) I2CSCLHR; // I2C SCL High Period Register
__sfr __at(0xFC) I2CSDAHR; // I2C SDA Hold Register
__sfr __at(0xFD) I2CDR;    // I2C Data Register
__sfr __at(0xFE) I2CSAR;   // I2C Slave Address Register
__sfr __at(0xFF) I2CSAR1;  // I2C Slave Address Register 1
// //----------------------------------------------------- //
// Flash and EEPROM Memory REGISTER                        //
// //----------------------------------------------------- //
__sfr __at(0xF1) FEMR;  // Flash and EEPROM mode register
__sfr __at(0xF2) FECR;  // Flash and EEPROM control register
__sfr __at(0xF3) FESR;  // Flash and EEPROM status register
__sfr __at(0xF4) FETCR; // Flash and EEPROM time control register
__sfr __at(0xF5) FEARL; // Flash and EEPROM address register low
__sfr __at(0xF6) FEARM; // Flash and EEPROM address register middle
__sfr __at(0xF7) FEARH; // Flash and EEPROM address register high
__sfr __at(0xEF) FEDR;  // Flash and EEPROM data register
__sfr __at(0xE7) FETR;  // Flash and EEPROM TEST register
// ==================================================================== //
// Flash and EEPROM Memory REGISTER                                     //
// ==================================================================== //
// (0xF1) FEMR;              // FECON        Flash and EEPROM mode register
#define FLASH_SEL (0x80)
#define FLASH_PGM_MODE (0x20)
#define FLASH_ERASE_MODE (0x10)
#define FLASH_PBUFF_SEL (0x08)
#define FLASH_OTPE_SEL (0x04)
#define FLASH_VERFY_MODE (0x02) // self verify mode
#define FLASH_CON_ENABLE (0x01)

// (0xF2) FECR;              // FECON        Flash and EEPROM control register
#define FLASH_BULK_ERASE (0x80 | 0x03)
#define FLASH_MODE_EXIT (0x30 | 0x03)
#define FLASH_START_ERASE_PGM (0x08 | 0x03)
#define FLASH_START_READ (0x04 | 0x03)
#define FLASH_RESET (0x01)
#define FLASH_PBUFF_RESET (0x02)
#define FLASH_FECR_INIT (0x03)

// (0xF3) FESR;              // FECON        Flash and EEPROM status register
#define FLASH_BUSY (0x80)
#define FLASH_VERIFY_OK (0x40)
#define FLASH_CRC_MODE (0x20)
#define FLASH_MWAIT_EN (0x10)
#define FLASH_IRQ (0x08)
#define FLASH_ST_PGM_MODE (0x04)
#define FLASH_ST_ERASE_MODE (0x02)
#define FLASH_ST_VERIFY_MODE (0x01)

// (0xE7) FETR;              // FECON        Flash and EEPROM test register
#define FLASH_LOCK_DISABLE (0x80)
#define FLASH_VPP_OUT_ENABLE (0x60)
#define FLASH_FULL_READ (0x08)
#define FLASH_PAGE_READ (0x00)
#define FLASH_X_FAST (0x04)
#define FLASH_Y_FAST (0x00)
#define FLASH_EVEN_ENABLE (0x02)
#define FLASH_ODD_ENABLE (0x01)
#define FLASH_VMARGIN_ENABLE (0x01)
// ==================================================================== //
// CRC                                                                //
// ==================================================================== //

#define CRC_CON *(volatile unsigned char xdata *)0x20E0 //

#define CRC_H *(volatile unsigned char xdata *)0x20E3     //
#define CRC_L *(volatile unsigned char xdata *)0x20E4     //
#define CRC_MNT_H *(volatile unsigned char xdata *)0x20E5 //
#define CRC_MNT_L *(volatile unsigned char xdata *)0x20E6 //

#define CRC_ADDR_START_M *(volatile unsigned char xdata *)0x20EB //
#define CRC_ADDR_START_L *(volatile unsigned char xdata *)0x20EC //

#define CRC_ADDR_END_M *(volatile unsigned char xdata *)0x20ED //
#define CRC_ADDR_END_L *(volatile unsigned char xdata *)0x20EE //

// Interrupt vectors of A94B114
#define CMP_VECT 0    // IE.0
#define EINT10_VECT 1 // IE.1
#define EINT11_VECT 2 // IE.2
#define EINT12_VECT 3 // IE.3
#define EINT_VECT 4   // IE.4

#define I2C_VECT 5      // IE1.0
#define USART_RX_VECT 6 // IE1.1
#define USART_TX_VECT 7 // IE1.2
#define CRC_VECT 8      // IE1.3
#define TIMER0_VECT 9   // IE1.4
#define TIMER1_VECT 10  // IE1.5
#define TIMER2_VECT 11  // IE1.6

#define ADC_VECT 12 // IE2.0
#define WDT_VECT 13 // IE2.1
#define BIT_VECT 14 // IE2.2
#define LVI_VECT 15 // IE2.3

// Interrupt en/dis control
#define sei() (EA = 1)
#define cli() (EA = 0)

#define cmpint_en() (CMP_INT_EN = 1)
#define eint10_en() (EINT10_INT_EN = 1)
#define eint11_en() (EINT11_INT_EN = 1)
#define eint12_en() (EINT12_INT_EN = 1)
#define eint_en() (EINT_INT_EN = 1)

#define i2cint_en() (I2C_INT_EN = 1)
#define uartrxint_en() (UART_RX_INT_EN = 1)
#define uarttxint_en() (UART_TX_INT_EN = 1)
#define crcint_en() (CRC_INT_EN = 1)
#define t0int_en() (T0_INT_EN = 1)
#define t1int_en() (T1_INT_EN = 1)
#define t2int_en() (T2_INT_EN = 1)

#define adcint_en() (ADC_INT_EN = 1)
#define wdtint_en() (WDT_INT_EN = 1)
#define bitint_en() (BIT_INT_EN = 1)
#define lviint_en() (LVI_INT_EN = 1)

#define cmpint_dis() (CMP_INT_EN = 0)
#define eint10_dis() (EINT10_INT_EN = 0)
#define eint11_dis() (EINT11_INT_EN = 0)
#define eint12_dis() (EINT12_INT_EN = 0)
#define eint_dis() (EINT_INT_EN = 0)

#define i2cint_dis() (I2C_INT_EN = 0)
#define uartrxint_dis() (UART_RX_INT_EN = 0)
#define uarttxint_dis() (UART_TX_INT_EN = 0)
#define crcint_dis() (CRC_INT_EN = 0)
#define t0int_dis() (T0_INT_EN = 0)
#define t1int_dis() (T1_INT_EN = 0)
#define t2int_dis() (T2_INT_EN = 0)

#define adcint_dis() (ADC_INT_EN = 0)
#define wdtint_dis() (WDT_INT_EN = 0)
#define bitint_dis() (BIT_INT_EN = 0)
#define lviint_dis() (LVI_INT_EN = 0)
// ==================================================================== //

#endif /* End of __A96G174_H_ */
/* --------------------------------- End Of File ------------------------------ */
